In a radio communication using a CDMA method, both a transmitting end and a receiving end use a same spread code to process a signal. Consequently, it becomes possible to transmit signals of plural channels by using a same frequency band at the same time at the transmitting end, and also, it becomes possible to extract only signals of intended channel from among the above-described plural channels at the receiving end.
By the way, as the spread code used in the CDMA method radio communication system, there is a PN code (Pseudo Random Code), or a GOLD code. Here, the GOLD code is a code sequence obtained by taking an exclusive OR of the two PN codes. Incidentally, the exclusive OR is referred to as XOR, hereinafter.
FIG. 23 is a view showing a configuration of a conventional PN code generator generating the PN code. Incidentally, in FIG. 23, the case is shown when the PN code generator is applied as a receiver to make a communication with a transmitter at a base station or the like, in the CDMA method.
In FIG. 23, a conventional PN code generator 220 is constituted by flip-flops 221a to 221d connected in series, an XOR circuit 222, and a memory 223. Incidentally, within the above, a linear feedback shift register is constituted by the flip-flops 221a to 221d and the XOR circuit 222. Besides, the PN code generator 220 having such a structure is the PN code generator of an M-sequence (Maximum-length sequence).
Operation of the conventional PN code generator 220 is described.
First, code patterns stored in the memory 223 are set to the respective flip-flops 221a to 221d, as an initial state. After that, the codes of the respective flip-flops 221a to 221c are shifted to the flip-flops 221b to 221d at the right-hand neighbor according to a clock signal CS outputted from a timer 224. At this time, the PN code PN is composed of the code outputted from the flip-flop 221d. Besides, the XOR between the code outputted from the flip-flop 221c and the code outputted from the flip-flop 221d is taken at the XOR circuit 222, and the result is outputted to the flip-flop 221a. 
FIG. 24 is a view showing a state transition of the flip-flops 221a to 221d. Incidentally, in the state transition diagram of FIG. 24, FF0 to FF3 are codes given to the flip-flops 221a to 221d at the respective phases. Further, an output code is a code outputted from the flip-flop 221d at each phase, and the PN code PN is composed of this code.
As shown in FIG. 24, the code patterns of the flip-flops 221a to 221d transit sequentially from the code pattern of FF0 to FF2 are zero, and FF3 is one at a first phase to the code pattern of FF0 and FF1 are zero, and FF2 and FF3 are one at a 15th phase. Next, at a 16th phase, it goes back to the state of the first phase, and the same state transition as the state transition from the first phase is repeated from the 16th phase. Namely, in the PN code generator 220 shown in FIG. 23, the PN code PN of “100010011010111” shown by the output code in FIG. 24 is generated repeatedly, and thereby, a cyclic PN code is to be generated.
Incidentally, in a radio communication using the CDMA method, it is required to despread a received data by generating the PN code having the same time waveform as the PN code used to spread the transmission data at the transmitting end. Consequently, in a receiver using the CDMA method such as a cellular phone, the phase where the PN code used at a transmitter of a base station, and so on, starts is detected, and thereafter, the PN code PN is generated from the detected phase.
In the conventional PN code generator 220, the PN code is generated from the detected phase by the following method.
Namely, the code pattern predetermined as an initial state is set to the flip-flops 221a to 221d, and then, the PN code PN is generated after the flip-flops 221a to 221d are operated until the code pattern becomes to be the one at the detected phase.
The operation of the receiver at the time of setting the code pattern at the detected phase is described with reference to FIG. 23.
At first, a synchronous detection circuit 225 detects a beginning phase of the PN code used when the CDMA signal CD is spread, from a signal of a channel for synchronous detection contained in the CDMA signal CD received at a receiving section 226 to output to a comparator 227. Next, the comparator 227 compares the beginning phase of the PN code PN detected at the synchronous detection circuit 225 and a counted value of the timer 224, and when the both value is matched, the comparator 227 outputs an initial value load signal LS to the PN code generator 220.
The PN code generator 220, to which the initial value load signal LS is inputted, sets the code pattern corresponding to the initial value load signal LS (for example, the code pattern at the first phase in FIG. 24) to the flip-flops 221a to 221d by reading out from the memory 223, or the like. After that, the PN code generator 220 starts the operation to shift the codes given to the flip-flops 221a to 221d as stated above.
In this manner, in the conventional PN code generator 220, the predetermined code pattern is set to the flip-flops 221a to 221d, and thereafter, the codes held by the flip-flops 221a to 221d are shifted, and thereby, the code pattern at the detected phase is set.
For example, when the code pattern at a 12th phase shown in FIG. 24 is specified to set, the code pattern at the first phase is set, and then, it is required to shift the codes of the flip-flops 221a to 221d for 11 times.
In FIG. 24, a case when a degree of the linear shift register (number of the flip-flops) is four is shown, but when the degree of the linear feedback shift register is N, the respective flip-flops hold “2N−1” pieces of code patterns repeatedly. The “2N−1” pieces of code patterns taken by the respective flip-flops are in different states respectively, and the same state does not exist. Consequently, the codes given to the flip-flops 221a to 221d must be shifted for the number of times corresponding to the difference between the initial phase and the detected phase, to set the code pattern at the detected phase.
Generally, the degree N of the linear shift register is large (for example, 20), and therefore, the number of times to shift the codes given to the flip-flops becomes very large to obtain the code pattern at the detected phase in the above-stated manner.
As described above, it takes a vast amount of time until the code pattern at the detected phase is set by using the linear feedback shift register to generate the PN code. Namely, in the conventional PN code generator 220, it takes a long time to generate the PN code PN at a random phase.
FIG. 25 is a view showing a configuration of a conventional PN code generator to solve these problems. Incidentally, in FIG. 25, the same reference numerals and symbols are used to designate the same and corresponding elements as in FIG. 23.
In FIG. 25, a PN code generator 240 has a structure that the codes at the respective phases outputted from the flip-flop 221d of the PN code generator 220 shown in FIG. 23 (the output code shown in FIG. 24), namely, the PN code PN is stored in a memory 241 in advance. Here, the codes at the respective phases are stored at continuous addresses of the memory 241 in order.
As an explanation of the concrete operation, at first, a synchronous detection circuit 242 detects a beginning phase of the PN code used at the base station when the CDMA signal CD is spread, from a signal of a channel for synchronous detection contained in the CDMA signal CD received at the receiving section 226, and determines the beginning phase of the PN code PN to be generated at the PN code generator 240. Next, the synchronous detection circuit 242 calculates a time CT representing a timing to generate the PN code PN at the determined phase (code first time), to output to a comparator 243.
The comparator 243 is inputted the code first time CT from the synchronous detection circuit 242, and then, reads out the time counted at the timer 244, and finds a time difference between the code first time CT and the time counted at the timer 244. Next, the comparator 243 outputs an address signal AS representing an address of the memory. 241 corresponding to the calculated time difference to the memory 241. Herewith, the code stored in the address specified by the address signal AS (namely, the PN code PN at the phase detected by the synchronous detection circuit 242) is outputted from the memory 241. Next, the comparator 243 increments the converted address, and outputs the address signal AS representing the incremented address to the memory 241. Herewith, the PN code PN which begins with the code stored in the converted address is outputted from the memory 241.
As stated above, every PN code PN outputted from the linear feedback shift register is stored in the memory 241 in advance, and thereby, the PN code PN can be generated immediately from the random phase, but the number of bits to be stored in the memory 241 becomes large. When the degree of the linear feedback shift register is N, the number of bits to be stored in the memory 241 becomes “2N−1”. Consequently, when the PN code PN having a long code length (=2N−1) is to be generated, there is a problem that the number of bits to be stored in the memory 241 becomes large.
The present invention is made in consideration with the above problems, and the object thereof is to minimize the number of bits to be stored in the memory as less as possible, and to generate the PN code immediately from the random phase.